A flash ADC comprises a set of comparators, each with a different threshold. The input to a comparator could be between 0 and 1 volt. If a signal comes in at 0.5 volts, the comparators that have a threshold of 0.5 volts or lower provide an output of 1, while the comparators having a threshold above 0.5 volts provide an output of 0. As such, the comparators provide an indication, based on their thresholds, of the input signal value.
For ADC comparators, the thresholds are normally linearly spaced with respect to each other, although this constraint is not necessary. An important constraint is that the thresholds be known to the downstream digital signal processor (DSP). For a bank of comparators arranged such that they are evenly and linearly spaced, such that the threshold voltage between any two thresholds is the same, the quality of the data conversion depends on the linearity of that spacing. An example implementation with 16 threshold levels would provide a data convertor of 4 bits (since 24=16). This would require 16 evenly spaced thresholds. If the thresholds are not evenly spaced, the effective resolution of ADC is lower than 16.
In order to obtain a better quality of ADC, it is important that the thresholds be spaced as linearly as possible. However, each one of those comparators is an imperfect analog circuit and it performs the comparison at a rising edge of the clock. Therefore, at the clock edge, it compares the input to the threshold, and if the input is above the threshold then the output is a 1, and if it is below the threshold the output is a 0.
Flash ADC comparators are analog circuits whose ideal input-output relationship can be described as:outputk(t)=sign(input(t)−thresholdk)  Equation 1
However the real-life, or non-ideal, behavior of the comparator introduces an offset, thereby shifting the kth threshold by an amount offsetk, as shown below.outputk(t)=sign(input(t)−thresholdk+offsetk)  Equation 2
It is desirable to remove, or “calibrate out” these offsets so that the thresholds can be known to the DSP.
There are two categories of calibration: foreground and background. Foreground calibration refers to a procedure performed in such a way as to disrupt the normal signal flow through the ADC, often by temporarily removing the normal ADC input signal and introducing a known calibration input signal. By doing so, during foreground calibration the system in which the ADC is performing the data conversion is not able to process the normal input signal. This disruption can sometimes be tolerated at certain times in the life cycle of the system with the ADC, perhaps for a brief time at power up.
Background calibration refers to a calibration procedure in which the normal signal flow of the system with the ADC is not disrupted in any way; the system can continue to process data from the ADC and expect the conversion performance to be within specified bounds and that the normal input signal is being converted.
Recall the input-output relationship of an analog comparator:outputk(t)=sign(input(t)−thresholdk+offsetk)  Equation 3
Where “k” is an index referring to the “kth” comparator. Thus, the “effective” threshold is at thresholdk−offsetk. For example, if a threshold of 0.1 is desired and there is an offset of 0.01, then the effective threshold is 0.11. Foreground calibration works by introducing a known input signal (usually equal to the desired threshold) and adjusting the threshold so that the offset is effectively removed. For convenience, assume that the foreground calibration occurs at t=0.outputk(0)=sign(thresholdk−(thresholdk+offsetk)+offsetk)=sign(0)  Equation 4
Here, “sign(0)” is shown as the comparator calibrated state since at this value, the comparator is exactly between a +1 and −1 output, so any arbitrarily small change in the input will force the comparator to be resolved.
In this manner, the offset of the comparator is removed by adding it to the desired ideal threshold of the comparator. So, setthresholdk=DesiredThresholdk+offsetk  Equation 5
There is still one important non-ideality missing from Equation 3, the variation in time of the offset, shown below in Equation 4.outputk(t)=sign(input(t)−thresholdk(t)+offsetk(t))  Equation 6
Foreground calibration can calibrate the threshold at a given point in time, but if the offsetk varies significantly with time, ADC performance will be degraded. In this case, background calibration is necessary, and so the following is needed:thresholdk(t)=DesiredThresholdk+offsetk(t)  Equation 7
It is, therefore, desirable to adjust thresholdk(t) in the background.